Design of modified reference phase modulation based boost chopper fed fifteen level stepped DC link hybrid converter

A new fifteen-level stepped DC to AC hybrid converter is proposed for Solar Photovoltaic (SPV) applications. A boost chopper circuit is designed and interfaced with the fifteen-level hybrid converters specific to Electric Vehicles’ Brushless DC Motor (BLDC) drive systems. In chopper units, the output of solar panels is regulated and stepped up to obtain the nominal output voltage. In the stepped DC-link hybrid converter configuration, fifteen-level DC-link voltage is achieved by the series-operated DC-link modules with reduced electrical energy compression. From the comprehensive structure, it is anecdotal that the proposed topology has achieved minimum switching and power loss. Elimination of end passive components highlights the merits of the proposed hybrid systems. The reduction of controlled power semiconductor switches and gate-firing circuits has made the system more reliable than other hybrid converters. From the extensive analysis, the experimental setup has reported that 7% reduction in harmonics and a 54% reduction in controlled power switches than the existing fifteen-level converter topologies. Mitigation of power quality issues in the voltage profile of a fifteen-level multilevel hybrid converter is achieved through the implementation of dsPIC digital-controller-based gate triggering circuits.

in the Cascaded Multilevel Inverter (CMLI), a boost chopper is generally used between the DC sources and H-bridges.However, the efficiency and handling of CMLI and Boost Cascaded Multilevel Inverter (BCMLI) configurations get degraded because of a higher number of controlled power switches and DC sources.Thus, certain modifications in conventional CMLI and BCMLI systems are envisioned based on the 15-level hybrid converter SPV-based charging system [25][26][27][28] .The proposed system introduces two isolated DC-to-DC and backend inverters for shaft load and auxiliary loads to reduce controlled power semiconductor switches and solar PV panels/sources.The nominal output voltage is obtained by introducing the boost chopper circuit in between the DC sources and DC link inverter -DC input voltage is boosted to the nominal voltage level by the boost chopper network.This reduces the number of DC sources and power switches, and using a three-level DC link chopper module provides the extended boost capability to the back-end inverter module.
The structure of the stepped DC link, DC to DC converter, is represented in "Introduction" section.The proposed hybrid inverter is presented in "Structure of 15-level boost hybrid converter system" section.The design of SPV with boost chopper for auxiliary load systems is addressed in Modes of operation section.Comparative analysis with traditional MLIs and hybrid converters is made in "Modified MCSPWM switching technique" section.The simulation and experimental results of three-level boosted 15-level hybrid converters are addressed in "Results and analysis" section.In conclusion, the observations and scope for further improvements are addressed.
The structure of cascaded multilevel inverter and boost cascaded multilevel inverter circuits are represented in Fig. 1a and b, respectively.With Fig. 1a and b as a reference, the required number of DC sources and controlled switches to develop a 15-Level AC output voltage in a Cascaded Multilevel Inverter is derived using the following Eqs.( 1) and ( 2).The number of solar PV panels/sources and controlled switches required to develop a 15-Level AC output voltage in boost cascaded multilevel inverter derived using the Eqs.( 3) and ( 4).

Structure of 15-level boost hybrid converter system
The design structure of the 15-level boost hybrid converter is illustrated in Fig. 2a.The system is developed with PV panels as DC sources, a DC-to-DC boost chopper, a hybrid circuit and a two-level voltage source inverter.The number of PV panels and the semiconductor switches required to develop a 15-Level hybrid converter is estimated through Eq. ( 5).
where, s is represents the input source (1)

Mode I and mode IX operation
In mode I and IX operation, all power semiconductor voltage-controlled MOSFET switches are operated in OFF condition.Hence, the output voltage is estimated at zero level.

Mode II and mode X operation
In mode II and X operations, the input voltage of 36 V is boosted to 48 V through the activation of DC-to-DC converter switch S a with the desired duty ratio and the switches of proposed multilevel DC link converter S 6 , S 7 , S 9 .The corresponding circuit for these operating modes is shown in Fig. 2b.

Mode III and mode XI operation
In mode III and XI operations, the input voltage of 72 V is boosted to 96 V through the activation of DC-to-DC converter switch S b , and the switches of proposed multilevel DC link converter switches S 5 , S 8 , S 9 .The equivalent circuit for these operating modes is shown in Fig. 2c.

Mode IV and mode XII operation
In mode IV and XII operations, the input 36 V is boosted to 48 V, 72 V is boosted to 96 V through the activation of DC-to-DC converter switch S a and S b , and the switches of proposed multilevel DC link converter switches S 6 , S 8 , S 9 .The corresponding circuit for the operating modes is illustrated in Fig. 2d.

Mode V and mode XIII operation
In mode V and XIII operations, the input voltages of 36 V are boosted to 48 V, 72 V is boosted to 96 V through the activation of DC-to-DC converter switch S c , and the switches of proposed multilevel DC link converter switches S 5 , S 7 , S 10 .The equivalent circuit for these operating modes is shown in Fig. 2e.At t = T ON5 , the DC-to-DC converter switch S c is activated.The boosted voltage across the inductor L 3 is expressed as in Eq. (6).
And the energy input to the inductor L 1 is expressed as Eq. (7).
At t = T OFF5 , the DC-to-DC converter switch S c is de-activated, and the typical output voltage of the boost- chopper III circuit can be expressed using Eq. ( 8). ( 6)  www.nature.com/scientificreports/And the energy consumed by the load is given by Eq. ( 9)

Mode VI and mode XIV operation
In mode VI and XIV operations, the input voltage of 36 V is boosted to 48 V, and 144 V is boosted to 192 V through the activation of DC-to-DC converter switches S a and S c , and the switches of proposed multilevel DC link converter switches S 6 , S 7 , S 10 .The equivalent circuit for these operating modes is shown in Fig. 2f.At t = T ON6 , the DC-to-DC converter switches S a and S c are activated.The energy input to the inductors is expressed using Eq.(10).
At t = T OFF6 , the DC-to-DC converter switches S a and S c are deactivated, and the current through inductors reduces gradually.The energy consumed by the load system is calculated by Eq. (11).
At t = T ON7 , energy input to the inductor L 2 is expressed and inductor L3 is expressed using Eq. (12).
At t = T OFF7 , the DC-to-DC converter switches S b and S c are deactivated.At this instant, energy can consume by the load system is calculated by Eq. (13).
At t = T ON8 , the DC-to-DC converter switches S a , S b and S c are turned ON and the current through inductors raises linearly.At this instant, the energy inputs to the inductors can be expressed by Eq. ( 14).
At t = T OFF8 , the DC-to-DC converter-controlled switches S a , S b and S c are turned OFF, and the current through inductors fall linearly.Thus, the energy transferred from the inductors to the DC-link module is given by Eq. ( 15). ( 8) From the Fig. 4c, it is inferred that the magnitude of 3rd, 5th, 7th and 9th order harmonics are 3 V, 2.8 V, 2 V and 2.7 V respectively.Hence the switching loss is 10.5 V, which is about 3%.Power Loss of the stepped DC link module is 20.5 V, thus the Total System Loss is 31 V. Load current of the system is 4.39 A for the rated current of 5 A. The average loss of the proposed system considered is 136 W. In the conventional systems, H-Bridge inverter switches are subjected to hard switching due to steady state DC link voltage across the switches in all time period.In the proposed system DC link voltage has zero crossing at every 10ms as shown in the Fig. 6b.The voltage stress across the inverter switches is reduced and hence the TSV is reduced. (

Modified MCSPWM switching technique
The entire system is operated optimistically through the modulation technique.The literature shows DC link systems can be triggered through phase modulation or level shift modulation 29,30 .In the proposed work, phase shift modulation techniques are adopted to operate the systems of DC link and inverter switches.Generally, carrier and modulating signals play a major role in pulse generation in the phase modulation schemes.The vertical carrier distribution techniques are defined as level shifted (LS-PWM), which includes phase disposition (PD-PWM), phase opposition disposition (POD-PWM) and alternative phase opposition disposition (APOD-PWM).In the proposed system, reference signal is modified from the sine wave.Modified reference signals are used as reference signal hence in the modified signal, elimination of harmonics profile is maximum.Authors have done a exact modification in the peak amplitude of the sine wave reference signal.
Modified reference signals are used as reference signals; hence, the elimination of the harmonics profile is maximum in the modified signal.As a researcher, the elimination or the reduction of hardware component play major design criteria.Optimizing techniques facilitate reducing the higher order harmonics to some extent of lower order harmonics.Selective harmonic elimination is achieved through the optimizing techniques adopted for the converter system.Figure 3 represents the Modified Reference Phase Opposing Disposition Pulse Width Modulation (MRPODPWM).
Mathematical expressions for the MRPOD-PWM switching scheme for DC link switching are formulated using space vectors.

Modulation index is expressed using equation
The output voltage of DC link module is given by equation where, V 1 is the peak value of fundamental voltage, V 2 is the peak value of fundamental voltage generated by the stepped DC link switches and Vdc is the DC link voltage provided by the asymmetrical source.
Modified reference signal is generated by calculating the sectors at each level.The procedure to calculate the sector points of the modified reference signal are given using equations The output voltage and current harmonics of the proposed system are analyzed for different amplitude modulation indices ( M a = 0.8, 0.95, 1.0 and 1.2) and frequency modulation indices ( M f = 180, 200 and 220).The proposed system reduced the harmonic content for M a = 1 and M f = 200.For developing the firing pulses of DC link switches, N level − 1 pattern of triangular signals are compared with sinusoidal reference signal.
When the magnitude of reference signal (V ref ) is greater than triangular signals (V tri1 , V tri2 and V tri3 ) the corresponding pulses p 1 , p 2 and p 3 are generated.

Results and analysis
To authenticate the operation of the proposed configuration, the complete system structure is pretended by means of the MATLAB-SIMULINK tool and the recital of the circuit was recorded.
The output voltage of the 15-level stepped DC to AC converter is shown in Fig. 4a.Each level of the output voltage is developed as per the logic behind the switching table.The time period of the output voltage is decided by the modulating signal utilized for the generation of PWM ON/OFF square waveforms.Harmonics analysis are made using the FFT algorithm 31,32 , and the THD profile of the output voltage is shown in Fig. 4b.From the analysis, it is inferred that the value of individual harmonics and THD are as per IEEE standard.Individual harmonics are analyzed and the order of the harmonics is represented in a graphical manner and the magnitude of individual harmonics is represented in Fig. 4c.From the analysis, it is inferred that the magnitude of 3rd, 5th, 7th and 9th order harmonics are 3 V, 2.8 V, 2 V and 2.7 V respectively.( 25) www.nature.com/scientificreports/control signals to the MOSFET driver circuit.The various features of microcontroller aid to achieve an effective control of the proposed system.The DC link module and H-bridge inverter systems are fabricated using IRF840 power MOSFET switches.Driver units consist of IR2110 Integrated Circuit (IC) and its biasing components and the isolation process is achieved by 6N135 IC.The technical specifications of IRF840 power MOSFET are entailed in Table 2. System specification is represented in Table 3.The proposed circuits are boost chopper unit, stepped DC link module, H-Bridge inverter module.13 controlled switches are utilized for the proposed system; 3 controlled switches for Boost chopper unit, 6 controlled switches for stepped DC link module and 4 controlled H-Bridge inverter module.IR2110 IC is used as gate driver unit, PWM pulses are obtained from the port A and B of IR2110 IC.Three IR2110 ICs (One for boost chopper unit, one for stepped DC link module, one for H-Bridge inverter module are utilized for the proposed system.Each channel is isolated by optocoupler ICs.Totally 13 PWM signals are generated from the controller and the each signal is given to optocoupler IC. 13 PWM signals from the optocoupler ICs are given to three gate driver ICs.Load current of the system is 4.39 A for the rated current of 5A.The average loss of the proposed system considered as 136 W. Hence the Efficiency of the Proposed system is 91.2% (Table 4).Each unit's performance is discussed.The hardware setup is designed with the following units, 1. Source units-Solar PV as illustrated in Fig. 7b and battery bank.The experimental output voltage waveform of the proposed 15-Level hybrid inverter system is measured using CRO, as shown in Fig. 8a.From the output waveform, it is inferred that the output voltage is synchronized with 15-Level (One Zero, 7 Positive, and 7 Negative Levels).
The waveforms of experimental output voltage and current of the proposed 15-Level hybrid inverter system are also measured using power quality analyzer YOKOGAWA, as shown in Fig. 8b.From the analysis, it is observed that the magnitude and the frequency of the output voltage waveform are 325 Vmax and 49.976 Hz respectively.Element 1 in Fig. 8a represents the 15-level output voltage across the load.Element 2 in Fig. 8b represents the 7-level output voltage across the load (If two sources are connected).Element 3 in Fig. 8b represents the switching pattern for the DC link switches.Element 4 in Fig. 8b represents the load current.
The results of the comparison between the proposed work with other similar works in the literature are summarized in Table 2.It is inferred the proposed hybrid inverter gives better results, as illustrated in Fig. 8c, which also projects the qualitative analysis of the proposed CDDCLC work.

Conclusion
Through this article, the authors communicate a single-phase 15-level DC-interface converter; to be used in solar-oriented Electric-Vehicle charging applications.The proposed analysis combines a DC-chopper circuit and inverter (H-connect) for efficient optimization of the controlled power semiconductor switches to accomplish the reduced harmonic profile.In comparison with H-bridge inverter systems, the proposed hybrid system works with condensed voltage stress; lessens number of switches and DC sources.The projected configuration requires only 3-DC sources for producing 15-level AC output.The proposed construction is suggested for economic power  www.nature.com/scientificreports/semiconductor switches used in SPV applications.Thus, MATLAB simulation and laboratory-prototype model prove the performance of the proposed ideology.

Figure 2 .
Figure 2. (a) Structure of 15-level hybrid converter.(b) Mode II and X operation.(c) Mode III and XI operation.(d) Mode IV and XII operation.(e) Mode V and XIII operation.(f) Mode VI and XIV operation.

Figure 6 .
Figure 6.(a) Block diagram of the 15-level hybrid converter system.(b) DC link voltage.(c) Source voltage (Vdc1).(d) Blocking voltage of the DC link switches.
15-level boost hybrid inverter is operated for XVI modes to get hold of the desired output voltage.The transition manner of the hybrid converter is described in Table1.Based on the switching table, the projected converter is operated at different modes as follows: Vol.:(0123456789) Scientific Reports | (2024) 14:2706 | https://doi.org/10.1038/s41598-024-52727-8www.nature.com/scientificreports/Modes of operation A
In the Proposed system, prototype model consists of rectifier units, boost chopper units, controller units, driver units, DC link and H-Bridge inverter units.Controller, Optocoupler and gate driver units required constant power supply.Controller, Optocoupler ICs required 5 V power supply and the Gate driver ICs required 12 V power supply.7805 Linear Regulator IC is utilized for Controller, Optocoupler units and 7812 Linear Regulator IC is utilized for Gate driver circuits.The authors have designed and implemented the prototype model with separate isolation for both the ICs. 6. Gate driver unit-Designed using gate driver ICs (IR2110).Driver units consist of IR2110 Integrated Circuit (IC) and its biasing components.Opto-coupler unit-Designed using optocoupler ICs-and the isolation process is achieved by 6N135 IC. 7. Opto-coupler unit-Designed using optocoupler ICs 8. Controller unit-Designed using controller ICs (dsPIC)

Table 4 .
Comparison of the proposed work with existing work.